The present invention relates generally to computer bus control, and more specifically, to opportunistic bus access latency.
Memory devices and bus signaling frequency has increased to speeds that require special calibration circuits and techniques to compensate for variations in signaling delays to ensure that data transitions arrive at deterministic arrival times. When multiple memory devices are connected together in “ranks” via a common bus to a controller, these techniques may be independently applied to each rank on the bus. A memory rank is a unique, independently addressable area of memory with a predetermined bit-width.
Typically, the calibration circuits are first run at power-up and then periodically to determine and configure a signal delay chain to adjust early signals to match the latest signal arrival. These delay configuration settings can differ widely between different ranks that share a common bus. The controller is configured with a prescribed “rank-to-rank” (R2R) delay, typically 2-4 memory clock cycles, as a worst-case time for rank delay configuration circuits to flush their state and for a new rank delay configuration to be established. Since the R2R delay is fixed for a given design, it results in a memory access latency penalty when access to a given rank is followed by an access to another memory rank, even if the delay configuration between the ranks is inconsequential.